ADT7463
http://onsemi.com
32
incorporates a feature called dynamic T
MIN
calibration. This
feature reduces the design effort required to program the
automatic fan speed control loop. For more information and
how to program the automatic fan speed control loop and
dynamic T
MIN
calibration, see the AN613 Programming
the Automatic Fan Speed Control Loop Application Note.
The second fan speed control method is manual fan speed
control which is described in the next paragraph.
Manual Fan Speed Control
The ADT7463 allows the duty cycle of any PWM output
to be manually adjusted. This can be useful if users wish to
change fan speed in software or want to adjust PWM duty
cycle output for test purposes. Bits <7:5> of Registers 0x5C
to 0x5E (PWM Configuration) control the behavior of each
PWM output.
Table 43. PWM1 TO PWM3 CONFIGURATION
(REG. 0X5C TO 0X5E)
Bit
Mnemonic
Description
<7:5>
BHVR
111 = Manual Mode
Once under manual control, each PWM output may be
manually updated by writing to Registers 0x30 to 0x32
(PWMx current duty cycle registers).
Figure 52. Control PWM Duty Cycle Manually with a
Resolution of 0.39%
VARY PWM DUTY
CYCLE WITH 8BIT
RESOLUTION
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8bit registers
that allow the PWM duty cycle for each output to be set
anywhere from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWM
MIN
register is
given by
Value(Decimal) + PWM
MIN
0.39
Example 1: For a PWM duty cycle of 50%,
Value(Decimal) + 500.39 + 128 Decimal
Value + 128 Decimal or 0x80
Example 2: For a PWM duty cycle of 33%,
Value(Decimal) + 330.39 + 85 Decimal
Value + 85 Decimal or 0x54
Table 44. PWM DUTY CYCLE REGISTERS
Register
Description
Default
0x30
PWM1 Duty Cycle
0xFF (100%)
0x31
PWM2 Duty Cycle
0xFF (100%)
0x32
PWM3 Duty Cycle
0xFF (100%)
By reading the PWMx current duty cycle registers, users
can keep track of the current duty cycle on each PWM
output, even when the fans are running in automatic fan
speed control mode or acoustic enhancement mode.
Operating from 3.3 V Standby
The ADT7463 has been specifically designed to operate
from a 3.3 V STBY supply. In computers that support S3 and
S5 states, the core voltage of the processor is lowered in
these states. If using the dynamic T
MIN
mode, lowering the
core voltage of the processor would change the CPU
temperature and change the dynamics of the system under
dynamic T
MIN
control. Likewise, when monitoring
THERM
, the THERM
timer should be disabled during these
states.
Dynamic T
MIN
Control Register (Reg. 0x36)
<1> V
CCP
LO = 1
When the power is supplied from 3.3 V STBY and the
V
CCP
voltage drops below the V
CCP
low limit, the following
occurs:
" Status Bit 1 (V
CCP
) in Status Register 1 Gets Set
" SMBALERT
Gets Generated If Enabled
" THERM
Monitoring Is Disabled. The THERM
Timer
Should Hold Its Value Prior To the S3 or S5 State
" Dynamic T
MIN
Control Is Disabled. This Prevents
T
MIN
from Being Adjusted Due To an S3 or S5 State
" The ADT7463 Is Prevented from Entering the
Shutdown State
Once the core voltage, V
CCP
, goes above the V
CCP
low
limit, everything gets reenabled and the system resumes
normal operation. Note that since other voltages can drop or
be turned off during a low power state, these voltage
channels set status bits or generate SMBALERT
s. It is still
necessary to mask out these channels prior to entering a low
power state using the interrupt mask registers. When exiting
the low power state, the mask bits can be cleared. This
prevents the device from generating unwanted
SMBALERT
s during the low power state.
XOR Tree Test Mode
The ADT7463 includes an XOR Tree Test Mode. This
mode is useful for incircuit test equipment at boardlevel
testing. By applying stimulus to the pins included in the
XOR Tree, it is possible to detect opens or shorts on the
system board. Figure 53 shows the signals that are exercised
in the XOR Tree Test Mode.
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